Method for designing a decoupling circuit

ABSTRACT

A method for designing a decoupling circuit for a source line of a LSI includes the steps of determining the capacitance of the decoupling capacitor based on the electric charge necessary for one cycle operation of the LSI and the allowable fluctuation of the source voltage, and determining the inductance of the source line based on the impedance of the decoupling capacitor and the allowable minimum multiplexing ratio of the source current by the decoupling capacitor.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a method for designing a decouplingcircuit and, more particularly, to a method suitable for designing adecoupling circuit for each of power source lines (power supply lines)of a plurality of semiconductor integrated circuits (LSIs) mounted on acommon multilayer printed circuit board.

(b) Description of the Related Art

Digital circuits generally generate unwanted electromagnetic fieldemissions (EMIs) from multilayer printed circuit boards. Most of theEMIs are generated from the signal transmission lines as well as fromthe power source lines constituting resonators together with the groundlayer of the PCB. This fact necessitates employment of a counter measurefor the EMIs in the power source line. It is generally effective to usea decoupling circuit for suppressing the EMIs.

For instance, in Patent Publications JP-A-10-97560 and JP-A-11-15870,effective areas for disposing capacitors therein for suppressing theEMIs are depicted on a drawing for the layout of the printed circuitboard. The methods described therein, however, have a disadvantage inthat the design for selecting the capacitance of the capacitors cannotbe specifically determined. In particular, in a design for designing apower source system including a main source line and a plurality ofbranch source lines each disposed for a corresponding LSI, most part ofthe higher-frequency current components in the operational current fordriving the LSI is supplied from the decoupling capacitors, and theelectric charge supplied therefrom differs depending on the circuitconfigurations and the operations of the internals of the LSIs. Thismeans that selection of the decoupling capacitor for each LSI ispreferably conducted for each of the LSIs while considering thecharacteristics of the each of the LSIs.

However, even if the circuit configuration of the LSI is known, thetechnique for determining the decoupling capacitor from the circuitconfigurations is vet to be determined. In short, there is no knowndesign theory by which the circuit designers or users specificallydetermine the decoupling capacitor. In addition, for a larger number ofLSIs disposed on a printed circuit board, it costs a larger amount oftime to determine the decoupling capacitors for the respective LSIs.

In a technique such as described in JP-A-9-139573, a planar power sourcelayer conventionally used for the printed circuit board is configured asrespective source lines each having a specific width to thereby increasethe impedance of the source line for supplying electric power to acorresponding LSI in a higher frequency range. This impedes to someextent higher-frequency current components from transferring through thesource lines on the printed circuit board, whereby the electromagneticfield emission from the power source line is suppressed.

In the described technique, it is necessary to determine the length ofthe power source line, differently from the case of the planar sourcelayer, because the power source line on the printed circuit board shouldhave as small a length as possible in view of the restriction from thepractical size etc. of the printed circuit board. However, the techniquefor determining the length of the source line is yet to be established.In view of the EMI reduction, a larger capacitance of the decouplingcapacitor and a larger impedance of the source line on the printedcircuit board are preferable due to a higher efficiency of decoupling.

For suppressing the higher-frequency current components flowing throughthe source line on the printed circuit board, it is also effective todetermine the inductance of the source line on the printed circuit boardfor the object LSI based on the characteristics of the object LSI aswell as determining the decoupling capacitor as described above. This isbecause the higher-frequency current components flowing through thesource line depend on the configuration and the circuit scale of theLSI. The design for layout of the source lines requires a large amountof design work in view of the large number of LSIs mounted on theprinted circuit board

SUMMARY OF THE INVENTION

In view of the above problems in the conventional technique, it is anobject of the present invention to provide a method for power sourcedecoupling in a printed circuit board mounting thereon a plurality ofLSIs, which is capable of allowing reduction of unwanted electromagneticfield emission from the source lines while reducing the amount of designwork for the decoupling circuit.

The present invention provides a method for designing a decouplingcircuit for a source line of a LSI to be disposed on a printed circuitboard. The method comprises the steps of determining a capacitance of adecoupling capacitor based on electric charge necessary for driving theLSI in a specified period and an allowable voltage fluctuation of asource voltage at a source terminal of the LSI, and determining aninductance of the source line based on an impedance of the decouplingcapacitor and a multiplexing ratio of the source current of the LSI bythe decoupling capacitor.

In accordance with the method of the present invention, a decouplingcircuit can be designed for the source line of the LSI with a reduceddesign work. The resultant decoupling circuit has a decoupling circuitwhich allows the source line and the decoupling capacitor to supply theelectric charge necessary for driving the LSI and an inductance of thesource line which allows an effective source decoupling for the LSI.

The above and other objects, features and advantages of the presentinvention will be more apparent from the following description,referring to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a general power source decoupling circuitto be designed for a source line of a LSI by the method of the presentinvention.

FIG. 2 is an equivalent circuit diagram of the decoupling capacitorshown in FIG. 1.

FIG. 3 is a block diagram of a design system for designing thedecoupling circuit of FIG. 1 according to an embodiment of the presentinvention.

FIG. 4 is a block diagram of the LSI library composer 13 shown in FIG.3.

FIG. 5 is a block diagram of the decoupling capacitor designing block 14shown in FIG. 3.

FIG. 6 is a block diagram of the source line designing block 15 shown inFIG. 3.

FIGS. 7A and 7B are graphs for showing the determination of theeffective impedance of the decoupling capacitor.

FIGS. 8A and 8B are sectional views of the printed circuit boards forshowing the layered structure thereof.

FIG. 9 is a top plan view of the printed circuit board for showing anexample of the source lines designed by the embodiment of the presentinvention.

FIG. 10 is a block diagram of another example of the library composershown in FIG. 3.

FIG. 11 is a block diagram of another example of the library composershown in FIG. 3.

FIG. 12 is a spectrum diagram of the source current for a LSI.

FIG. 13 is a block diagram of another example of the source linedesigning block shown in FIG. 3.

FIG. 14A is a perspective view of a portion of the printed circuit boardfor showing the parasitic inductance of connection between thedecoupling capacitor and the ground layer, and

FIG. 14B is an equivalent circuit diagram of the decoupling capacitorand the parasitic inductance.

FIG. 15 is a circuit diagram of a decoupling circuit designed by themodified embodiment of the present invention shown in FIG. 13.

PREFERRED EMBODIMENTS OF THE INVENTION

Now, the present invention is more specifically described with referenceto accompanying drawings, wherein similar constituent elements aredesignated by similar or related reference numerals.

Referring to FIG. 1, a decoupling circuit for a source line to bedesigned by the method of the present invention includes a decouplingcapacitor 52 connected in parallel with an object LSI 51 between asource line 53 and a ground line 61, and a decoupling inductor (Ld)connected in series with the LSI 51 and formed by the structure of thesource line 53. The source lines 53 carries current Ips supplied from apower source 54, whereas the decoupling capacitor 52 supplies a currentIc to the LSI during a short interval of the operation thereof. Themethod of the present invention determines the electric parameters ofthe decoupling capacitor 52 and the inductor 53.

Referring to FIG. 2, the decoupling capacitor 52 shown in FIG. 1 in facthas a serial electric elements including a capacitance 57, an equivalentserial resistance 58 and an equivalent serial inductance 59, the valuesof which are determined by the method of the present invention.

Referring to FIG. 3, a decoupling circuit design system for designingthe decoupling circuit of FIG. 1 according to an embodiment of thepresent invention includes a LSI library 10, a capacitor library 11, aprinted circuit board (PCB) library 12, a LSI library composer 13, adecoupling capacitor designing block 14, and a source line designingblock 15, and generates the design results of a decoupling circuit suchas shown in FIG. 1. Information stored in each of the libraries 10, 11and 12 can be updated to and/or added with new information.

The LSI library 10 stores therein information for a variety of objectLSIs to be mounted on the PCB, the information including part number(LSI code), source terminal, source voltage VDD, minimum frequency fminand maximum frequency fmax of the design frequency, electric charge “Q”supplied to the object LSI in one operational cycle, average currentIave etc. of each of the object LSIs. If the object LSI includes aplurality of source terminals, these data are stored for each of thesource terminals.

The capacitor library 11 stores therein information for a variety ofexisting types of capacitors, the information including part name,capacitance “C”, equivalent serial resistance R_(C), equivalent serialinductance L_(C) for each of the existing capacitors.

The PCB library 12 stores therein information for a variety of PCBs,including layered structures thereof, the thicknesses of the conductorlayers, thickness, dielectric constant and relative permeability of eachof insulator layers, minimum width of the source line for a unit currentin the PCB etc. The layered structure of the LSI determines thedecoupling inductance per unit length of the source line 53.

The LSI library composer 13 calculates parameters such as minimumfrequency “fmin” and maximum frequency “fmax” of the source current,electric charge “Q” used in one cycle operation, average current “Iave”etc. of a LSI to be mounted on the PCB. The LSI library composer 13stores in the LSI library 10 these parameters of the LSI in connectionwith the respective source voltages VDD, part names and source terminalsthereof.

Referring to FIG. 4, the LSI library composer 13 includes a waveforminput section 17, design frequency determining section 18, chargecalculating section 19, a LSI library recording section 20, and deliversits outputs to the LSI library 10 for storage.

The decoupling capacitor designing block 14 determines the capacitanceof the decoupling capacitor based on the electric charge Q and anallowable fluctuation (or voltage drop) ΔV of the source voltage.Referring to FIG. 5, the decoupling capacitor designing block 14includes a voltage fluctuation input section 21, a capacitancecalculating section 22, a retrieving section 23 and a judgement section24, and delivers its outputs as capacitor information 38.

The source line designing block 15 determines the length and width ofthe source line for an object LSI in the PCB based on the impedancecharacteristics of the decoupling capacitor 52 prepared by thedecoupling capacitor designing section 14 and an allowable multiplexingratio of the decoupling capacitor 52. The term “multiplexing ratio” asused herein means the ratio of the current Ic supplied from thedecoupling capacitor to the current Ips supplied through the source lineduring a short interval.

Referring to FIG. 6, the source line designing block 15 includes amultiplexing ratio setting section 25, an inductance calculating section26, width determining section 27, an inductance per unit lengthcalculating section 28, a length calculating section 29, a lengthexamining section 30 and a judgement section 31, and delivers thedecoupling circuit design data 16.

In FIG. 4, the waveform input section 17 inputs the waveform of thesource current for the object LSI in one operational cycle thereof basedon the results of simulations or experiments. The design frequencydetermining section 18 determines the minimum frequency fmin and themaximum frequency fmax of the design frequency of the object LSI. Thedesign minimum and maximum frequencies are determined either by thefrequency band (between 30 MHz and 1 GHz) of the regulated EMI(electromagnetic interference) itself or by the regulated frequency bandin consideration of the operational frequency f0 of the object LSI. Morespecifically, if the operational frequency f0 is equal to or above thestandard frequency (30 MHz), the operational frequency f0 is used as theminimum frequency fmin and the maximum frequency fmax is set at 1 GHz.On the other hand, if the operational frequency f0 is lower than thestandard frequency 30 MHz, the standard frequency is used as the minimumfrequency and the maximum frequency is set at 1 GHz. This is because itis not necessary to consider the frequency range that is above or belowthe regulated frequency band, and because most part of the spectrum ofthe electromagnetic field emission measured as the EMI appears atfrequencies which are integral multiples of the operational frequency f0and thus the EMI below the operational frequency can be neglected.

The charge calculating section 19 calculates electric charge “Q”necessary for one cycle operation of the LSI based on the waveform ofthe source current for a single clock cycle input by the waveform inputsection 17. The calculated electric charge “Q” is the total electriccharge of the LSI injected through the source terminal to the LSI. TheLSI library recording section 20 registers the parameters including theminimum frequency fmin, the maximum frequency fmax, the electric charge“Q” necessary for one cycle operation and the source voltage VDD of anew object LSI in the LSI library 10 when the new LSI is to beregistered. These parameters are registered in connection with the partnumber and the source terminal of the LSI.

The decoupling capacitor designing block 14 determines the capacitanceof the decoupling capacitor based on the electric charge “Q” and theallowable voltage fluctuation ΔV of the source voltage.

In the above operation of the decoupling capacitor designing block 14,the voltage fluctuation input section 21 first inputs the allowablefluctuation ΔV. The decoupling capacitor 52 to be used herein must havea sufficient capacitance necessary for supplying the total electriccharge which is sufficient to drive the LSI.

The capacitance calculating section 22 calculates the minimumcapacitance of the decoupling capacitor based on the ratio of theelectric charge “Q” to the allowable fluctuation ΔV.

The retrieving section 23 retrieves from the capacitor library 11 acapacitor having the minimum capacitance among the capacitors eachhaving a capacitance above the ratio Q/ΔV. If such a capacitor issuccessfully retrieved from the capacitor library 11, the judgmentsection 24 determines the retrieved capacitor as the desired decouplingcapacitor. On the other hand, if such a capacitor is not retrieved fromthe capacitor library 11, the judgement section 24 instructs the voltagefluctuation input section 21 to revise the allowable fluctuation ΔV. Thecapacitance of the decoupling capacitor is thus determined.

The source line designing block 15 of FIG. 6 determines the length andthe width of the source line necessary for decoupling the source linebased on the impedance characteristic of the decoupling capacitordetermined by the decoupling capacitor designing block 14 and anallowable minimum multiplexing ratio (N) of the decoupling capacitor.

For an effective decoupling of the source line, the current I_(PS)flowing through the inductor or source line 53 in FIG. 1 must besufficiently lower than the current I_(C) flowing through the decouplingcapacitor 52. The multiplexing ratio setting section 25 sets anallowable minimum multiplexing ratio “N”, which may be 10 for apractical use, for example.

The inductance calculating section 26 calculates the inductance of thesource line based on the impedance Z_(C)(f) of the decoupling capacitorso that the ratio of the current spectrum I_(C)(f) flowing through thedecoupling capacitor 52 to the current spectrum Ips(f) flowing throughthe inductor 53 in the design frequency range between fmin and fmax isequal to or above the allowable minimum multiplexing ratio N. Thedecoupling capacitor used herein is that determined by the decouplingcapacitor designing block 14.

More specifically, an inductance satisfying the following relationship:

Ic(f)≧N×Ips(f)  (1)

is obtained as the inductance of the source line for the frequency “f”residing in the design frequency range between fmin and fmax, i.e., forfmin≦f≦fmax.

In a practical calculation, the relationship (1) can be satisfied if thefollowing relationship:

2πf×L≧N×|Zc(f)|  (2)

holds between the impedance of the source line 2πf×L and the impedanceZc(f) of the decoupling capacitor for fmin≦f≦fmax.

The inductance of the inductor, i.e., the source line 53 is determinedas follows. Referring to FIGS. 7A and 7B, wherein both the abscissa andordinate are plotted with logarithmic scales, curve 32 corresponds tothe absolute value of the impedance Zc(f) of the decoupling capacitor,line 33 corresponds to the absolute value 1/(2πf×C) of the impedancedetermined by the capacitance “C” of the decoupling capacitor, and line34 corresponds to the absolute value 2πf×Lc of the impedance determinedby the equivalent serial inductance Lc of the decoupling capacitor.

The absolute value |Veff(fmin)| of the effective impedance of thedecoupling capacitor at the minimum frequency fmin is selected from theimpedances 1/(2π×fmin×C) shown at point 35 and 2π×fmin×Lc as a higherone of them. The inductance L of the source line is calculated from theabsolute value |Veff(fmin)| (at point 35) of the effective impedance ofthe decoupling capacitor as follows:

L=N×|Zeff(fmin)|/(2π×fmin)  (3)

Line 37 in each of FIGS. 7A and 7B corresponds to the absolute value2π×f×L of the impedance of the source line, passes point 36 whichcorresponds to N×|Zeff(fmin)|, and has a gradient equal to the gradientof line 34. Thus, the relationship (2) can be satisfied at any frequencywithin the design frequency range.

The width determining section 27 in FIG. 6 determines the line width Wof the source line based on the average current Iave of the object LSIregistered in the LSI library 10 and the minimum line width (k) of thesource line for per unit current registered in the PCB library 12. Theline width W is determined as follows:

W≧k×Iave  (4).

The inductance per unit length calculating section 28 calculates theinductance per unit length (Lunit) of the source line which isdetermined by the layer structure, line thickness, dielectric constant,permeability, and the width “W” of the source line of the PCB. The layerstructure of the PCB is exemplified in FIGS. 8A and 8B. The source line53 may be disposed on the top surface of a dielectric layer 39 having abottom surface in contact with a grounded conductor layer 40, as shownin FIG. 8A, or may be sandwiched between first surfaces of a pair ofdielectric layers 39 each having a second surface in contact with agrounded conductor layer 40, as shown in FIG. 8B. In either case, theinductance per unit length (Lunit) of the source line can be calculatedbased on the structure of the PCB.

The length calculating section 29 calculates the length (lp) of thesource line based on the inductance L obtained by the inductancecalculating section 26 and the inductance per unit length (Lunit), asfollows:

lp=L/Lunit  (5).

The length examining section 30 examines whether the length lp of thesource line calculated by the length calculating section 29 is longerthan the maximum length Lmax of the source line prescribed beforehand.The maximum length Lmax is determined based on the wavelength λcorresponding to an uppermost frequency (fend), which is defined laterand may be fmax, and a maximum factor α for the source line as follows:

lmax=α×λ  (6).

The user can arbitrarily determine the maximum factor α for the sourceline.

The width and the length of the source line are thus determined.

The information for the decoupling capacitor and the width and length ofthe source line as obtained is delivered as the decoupling circuitdesign data 16 from the source line designing block 15, as shown in FIG.3. The thus obtained decoupling circuit design data 16 is delivered foreach of the source lines of the object LSIs, and includes all thenecessary information for designing the decoupling circuits. Thedecoupling circuit design data 16 includes part number, capacitance C,equivalent serial resistance Rc, equivalent serial inductance Lc etc.for the decoupling capacitor as well as the layered structure of thePCB, thickness “t” of the conductor layer therein, width “W” and thelength lp of each of the source lines etc. The decoupling circuit designdata 16 is supplied to a CAD system for layout design, which operatesfor the automated layout design for the source lines of all the LSIs tobe disposed on the PCB.

FIG. 9 shows an example of such layout design output from the CADsystem. The layout of LSIs 51 and the main source line 41 are manuallydetermined by the user. Each branch source line 53 as well as eachdecoupling capacitor 52 is determined by the CAD system. In thisexample, each source line 53 has a zigzag structure for achieving thedesired length lp of the source line which conforms to the desiredinductance of the source line. The decoupling capacitor 52 is connectedat the node connecting the source line 53 and the source terminal of theLSI.

Referring to FIG. 10, there is depicted a modification of the LSIlibrary composer 13 shown in FIG. 4. The modified LSI library composer13A includes a frequency input section 43 and an average current inputsection 44 instead of the waveform input section 17 in the LSI librarycomposer 13, and has other configurations similar to those of the LSIlibrary composer 13.

The frequency input section 43 inputs the operational frequency f0 ofthe LSI to be disposed on the PCB, whereas the average current inputsection 44 inputs the average current Iave flowing through the sourceterminal of the LSI, both based on the operation by the user. The designfrequency determining section 18 determines the minimum and maximumfrequencies of the object LSI based on the operational frequency f0. Thecharge calculating section 19 determines the electric charge “Q”necessary for one cycle operation of the LSI based on the clock periodof the LSI, which is reciprocal of the operational frequency f0, and theaverage current Iave, as follows:

Q=Iave/f0  (7).

Referring to FIG. 11, a further modification of the LSI librarycomposer, designated by numeral 13B, includes a current spectrumcalculating section 45, a current factor calculating section 46 and atotal current calculating section 47, in addition to the sections 17 to20 in the LSI library composer 13 shown in FIG. 4.

The current spectrum calculating section 45 calculates the spectrum ofthe source current of the object LSI. Referring to FIG. 12, the sourcecurrent of the LSI includes a zeroth-order current component having theoperational frequency f0, a first order current component having a firstorder frequency f1 which is twice the operational frequency f0, secondand higher order components having a second and higher order frequenciesf2, f3, . . . , which are integral multiples of the operationalfrequency f0. These frequencies f0, f1, f2, . . . are separated intothree frequency bands including a first band lower than the minimumfrequency fmin as described before, a second band between the minimumfrequency fmin and the uppermost frequency fend, and a third band higherthan the uppermost frequency fend.

The uppermost frequency fend may be determined equal to the maximumfrequency fmax as described before or may be a frequency fk at which thesource current has a current component I(fk) lower than a thresholdprescribed by the user.

The spectrum components between f0 and fend are added to obtain asubstantially total current in the design frequency as follows:$\begin{matrix}{\sum\limits_{{f0} \leq {fn} \leq {fend}}{I({fn})}} & (8)\end{matrix}$

The spectrum components between fmin and fend are also added to obtain ahigher-frequency current component as follows $\begin{matrix}{\sum\limits_{{f\quad \min} \leq {fn} \leq {fend}}{I({fn})}} & (9)\end{matrix}$

 A current factor β is defined here by the higher-frequency currentcomponent divided by the substantially total current as follows:$\begin{matrix}{\beta = \frac{\sum\limits_{{f\quad \min} \leq {fn} \leq {fend}}{I({fn})}}{\sum\limits_{{f0} \leq {fn} \leq {fend}}{I({fn})}}} & (10)\end{matrix}$

 The current factor β means the ratio of the higher-frequency currentcomponents to the total current in the source current of the LSI.

In this example, the electric charge “Q” necessary for one cycleoperation of the LSI is obtained as the product of the total electriccharge supplied through the source terminal in one operational cycle bythe current factor β.

Referring to FIG. 13, a modification of the source line designing block,designated by numeral 15A, includes a connection inductance calculatingsection 63 in addition to the sections 25 to 31 in the source linedesigning block 15 shown in FIG. 6. The connection inductancecalculating section 63 calculates the equivalent inductance Lg of theconnection between the terminal of the decoupling capacitor 52 and theterminal of the ground layer of the PCB.

Referring to FIG. 14A, the decoupling capacitor 52 has a first terminal64 mounted on a terminal layer 49, which is connected to the groundlayer 61 of the PCB through a via hole 60. The terminal layer 49 and thevia hole 60 in combination add a connection inductance Lg (62) to thedecoupling capacitor 52, as shown in FIG. 14B. That is, the decouplingcapacitor 52 has a capacitance C, equivalent serial resistor Rc and anequivalent serial inductance (Lc+Lg).

The relationship (2) is replaced herein as follows:

2πf×L≧N×|Zpc(f)| (for fmin≦f≦fmax)  (11)

wherein Zpc(f) is the sum of the impedances of the decoupling capacitor52 and the connection between the decoupling capacitor 52 and the groundlayer 49.

The absolute value |Zeff(fmin)| of the effective impedance at theminimum frequency is defined as one of the absolute impedance1/(2π×fmin×C) of the capacitance of the decoupling capacitor and theimpedance of the sum of the equivalent inductances Lc+Lg, which ishigher than the other of the two impedances. The information for theequivalent inductance Lg of the connection is supplied through theconnection inductance input section 63. In an alternative, theequivalent inductance Lg may be stored in the PCB library 12.

Since the above embodiments are described only for examples, the presentinvention is not limited to the above embodiments and variousmodifications or alterations can be easily made therefrom by thoseskilled in the art without departing from the scope of the presentinvention.

What is claimed is:
 1. A method for designing a decoupling circuit for asource line of a LSI to be disposed on a printed circuit board, themethod comprising the steps of determining a capacitance of a decouplingcapacitor based on electric charge necessary for driving the LSI in aspecified period and an allowable voltage fluctuation of a sourcevoltage at a source terminal of the LSI, and determining an inductanceof the source line based on an impedance of the decoupling capacitor andan allowable minimum multiplexing ratio of a source current of the LSIby the decoupling capacitor.
 2. The method as defined in claim 1,wherein the electric charge is calculated from an integral of a waveformof the source current.
 3. The method as defined in claim 1, wherein theelectric charge is calculated based on an average source current and anoperational frequency of the LSI.
 4. The method as defined in claim 1,further comprising the step of calculating a first sum ofhigher-frequency current components and a second sum of total currentcomponents of the source current based on a spectrum of the sourcecurrent, wherein the electric charge is calculated based on a ratio ofthe first sum to the second sum and a total charge passing through thesource terminal to the LSI.
 5. The method as defined in claim 4, whereineach of the higher-frequency components has a frequency higher than aminimum design frequency.
 6. The method as defined in claim 1, whereinthe inductance of the source line is calculated based on an effectiveimpedance of the decoupling capacitor and the multiplexing ratio, theeffective impedance being selected from an absolute value of animpedance corresponding to the capacitance of the decoupling capacitorat a minimum design frequency and an absolute value of an impedancecorresponding to a serial inductance of the decoupling capacitor at theminimum design frequency, as a larger one of both the impedancescompared to the other of both the impedances.
 7. The method as definedin claim 6, wherein the serial inductance of the decoupling capacitorincludes an equivalent inductance of the decoupling capacitor and anequivalent inductance of a connection between a ground layer and thedecoupling capacitor.
 8. The method as defined in claim 1, furthercomprising the step of determining a length of the source line from theinductance of the source line based on width and thickness of the sourceline and thickness of dielectric constant and permeability of adielectric layer.
 9. The method as defined in claim 1, wherein thespecific period is one clock cycle of the LSI.